| Autor: |
Bheda, Rishiraj A., Beu, Jesse G., Railing, Brian P., Conte, Thomas M. |
| Zdroj: |
2012 IEEE 20th International Symposium on Modeling, Analysis & Simulation of Computer & Telecommunication Systems; 1/ 1/2012, p261-268, 8p |
| Abstrakt: |
Many new non-volatile memory technologies have been considered as a future scalable alternative to DRAM. Memory technologies such as MRAM, FeRAM, PCM have emerged as the most viable alternatives. But these memories have limited wear endurance. Practically realizable main memory systems employing these memory technologies are possible only if the wear across these memories is reduced as well as uniformly distributed. Limited endurance has resulted in extensive wear leveling research with the goal of uniformly distributing write traffic throughout available physical memory. Basic support for wear leveling is already present in existing systems, in the form of operating system paging. The Operating System (OS) changes virtual to physical translations over time. As a result, write traffic is naturally spread out. Proper evaluation of the need for wear leveling as well as the impact of the corresponding technique must take this phenomenon into account. Ignoring the effect of OS paging mechanism can result in highly inaccurate memory lifetime extrapolations. We demonstrate through simulation results, the effects of inaccurate extrapolations in the absence of OS modeling. Accurate memory lifetime simulation can take from many months to years. Although sampling techniques are commonly employed for speedup, our results show that naïve extrapolation techniques can lead to wildly different lifetime estimates. We show how sampling can be accurately applied by accounting for the different components in the write stream observed by main memory. Finally, we present a heuristic to quickly estimate memory lifetime for a given application. [ABSTRACT FROM PUBLISHER] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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