| Autor: |
Liu, Xuelian, Zia, Aamir, LeRoy, Mitchell R., Raman, Srikumar, Clark, Ryan, Kraft, Russell, McDonald, John F. |
| Zdroj: |
2012 IEEE 15th International Symposium on Design & Diagnostics of Electronic Circuits & Systems (DDECS); 1/ 1/2012, p159-162, 4p |
| Abstrakt: |
This paper describes the capacitorless 1-transistor (1T) DRAMs exploits the floating body (FB) effect of Fully depleted (FD) SOI devices, where the transistor body is used as a charge storage node. A novel three-tier, 3D, 1T embedded DRAM is presented that can be vertically integrated with the microprocessor achieving low cost, high density on-chip main memory. A 394Kbits test chip is designed and fabricated in a 0.15um fully depleted SOI CMOS process. The measured retention time under holding conditions is higher than 10ms. In the continuous read mode, every read should be followed by a refresh. The test chip is designed to work with an access time of 50ns and operates at 10MHz. [ABSTRACT FROM PUBLISHER] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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