| Autor: |
Haizheng Guo, Kwasniewski, Tad |
| Zdroj: |
2012 25th IEEE Canadian Conference on Electrical & Computer Engineering (CCECE); 1/ 1/2012, p1-4, 4p |
| Abstrakt: |
A delay-locked loop (DLL) based fractional-N frequency synthesizer with a programmable injection clock is presented. The proposed DLL architecture overcomes the integer-N limitation of the conventional DLL-based frequency multiplier, and can achieve small frequency step while maintaining low jitter accumulation. The frequency multiplication part is achieved by using either edge-combing DLL or MDLL structure, while the programmable injection clock is obtained by employing a DLL-based digital-to-phase converter. Based on the proposed architecture, a frequency synthesizer with 50MHz–1.3GHz output frequency tuning range has been design in 0.18µm CMOS technology. And a multiplication ratio of MN / (N+k) can be obtained, in which M, N and K are programmable. The DLL achieves around −42dB reference spur level. [ABSTRACT FROM PUBLISHER] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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