| Autor: |
Kruus, H., Ubar, R., Ellervee, P., Gorev, M., Pesonen, V., Devadze, S., Orasson, E., Brik, M., Min, M., Annus, P., Kruus, M., Meigas, K. |
| Zdroj: |
2012 13th Biennial Baltic Electronics Conference; 1/ 1/2012, p85-88, 4p |
| Abstrakt: |
We propose a benchmark suite for systematic evaluation of efficiency of new CAD and test algorithms. The suite consists of a set of high performance signal processors. Differently from all other existing benchmark suites, all the member processors of this family perform the same function, but are implemented in different ways, differing mainly in sharing of computing resources. The circuits are characterized by different structural complexities measured in the number of reconvergent fan-outs. The latter feature has the main impact to the testability of circuits, influencing directly on the efficiency of test tools and on the quality of the given test set. The main advantage of the benchmark suite, compared to the existing ones, relies in the possibility to create systematic dependencies of the efficiency of test algorithms or test quality as a function of the structural complexity of circuits. [ABSTRACT FROM PUBLISHER] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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