| Autor: |
Islam, Aminul, Imran, Ale, Hasan, Mohd. |
| Zdroj: |
2011 International Conference on Multimedia, Signal Processing & Communication Technologies; 1/ 1/2011, p99-102, 4p |
| Abstrakt: |
This paper presents a technique to mitigate the impact of threshold voltage variation on digital circuit. The proposed technique increases logic depth by incorporating a transmission gate (TG) in the critical path of full adder architecture. It offers 1.04× improvement in EDP (energy-delay product) incurring 1.04× penalty in tp (propagation delay) at 350 mV with 200 fF CLoad (load capacitance) connected at SUM and CARRY outputs. It proves its robustness against process variations by offering 1.19× improvements in tp variability and 1.38× improvements in EDP variability. These improvements are achieved at the expense of two extra transistors used in a TG. [ABSTRACT FROM PUBLISHER] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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