| Autor: |
Ore, Siew Hoon, Kian Yeow Gan, Tamil, Jonathan, Suthiwongsunthorn, Nathapong, Chungpaiboonpatana, Surasit |
| Zdroj: |
2011 IEEE 13th Electronics Packaging Technology Conference; 1/ 1/2011, p714-721, 8p |
| Abstrakt: |
We have developed solutions for the quick assessment of the D2-FBGA thermal performance to meet the rising demands for shorter cycle times to provide thermal solutions. D2-FBGA package has multiple devices packaged within the same footprint which can result in higher temperatures. Thus thermal management and characterization of stacked die packages is vital. We have designed a user friendly tool that provides a quick estimation of the junction to ambient thermal resistance of the D2-FBGA package under JEDEC test conditions (JESD 51-2 and JESD 51-6). Results can be obtained within minutes by a click of a button after the simple entry of key package and environmental data. This tool significantly reduces the time for thermal evaluation; from hours or days for conducting full Computational Fluid Dynamics (CFD) simulations, to minutes by using the tool. It can also be used for upfront thermal design, to assess the thermal impact due to changes in various package factors such as package size, die sizes, die powers, die attach material and thickness, solder balls under the die area and substrate details. The tool can also assess the impact due to changes in wind speed and test board. With these features, the tool can quickly estimate if the package meets the thermal requirement, and if it fails, quickly identify potential thermal solutions. [ABSTRACT FROM PUBLISHER] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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