| Autor: |
Li, Gang, Hanke, Ulrik, Cheng, Zaijun, Min, Deokki, San, Haisheng, Chen, Xuyuan |
| Zdroj: |
2011 11th IEEE International Conference on Nanotechnology; 1/ 1/2011, p496-499, 4p |
| Abstrakt: |
SiO2/Si3N4 double-layer dielectric stacks, instead of single dielectric layer, have been investigated to mitigate charge accumulation in the dielectric for the purpose of high reliable capacitive microelectromechanical switch. Two kinds of double-dielectric-layers with different thickness ratios are structured, and SiO2 single-layer dielectric structure is also fabricated for comparison. The charge injection kinetics in the dielectric layer has been investigated by performing C-V measurements on metal-insulator-semiconductor (MIS) capacitor structure instead of an actual switch. The experiment results generally show that low charge accumulation has been achieved by using double-layer dielectric stacks. More in detail, the experiment results further show that the charge accumulation behaviors varied greatly with the different thickness ratio of Si3N4 to SiO2. With same positive dc bias voltage for charge injection, we found that net negative charge accumulated in the thin-oxide MNOS structure and net positive charge accumulated in the thick-oxide MNOS structure as the electron injection is suppressed by the thick oxide. It can be anticipated that the charge accumulation in the switch dielectric can be minimized by optimizing the thickness ratio of double-layer dielectric. [ABSTRACT FROM PUBLISHER] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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