| Abstrakt: |
Low power has become a burning issue in modern VLSI design. To deal with this problem, the multiple-supply voltage (MSV) is a technique widely applied to a design to reduce its power consumption. However, there exist several challenges in implementing Multi-Voltage designs, which includes floorplanning, level-shifter placement, and power planning [5]. Among these challenges, placement of level shifters has direct impacts on the chip area, total wirelength, and power planning. Although several works considering MSV driven floorplanning have been proposed, they do not actually place level shifters in their flows, which makes their results unrealistic. Yu et al. [19] first proposed a methodology to place level shifters during floorplanning. But, level shifters are inserted in the whitespace of a chip, which would increase wirelength of long wires and make power planning more difficult. Thus, in this paper, we first propose two ways to allocate regions for level shifters during floorplanning, and then give a two-stage approach to place these level shifters at proper locations. The experimental results reveal that the wirelength is underestimated if we do place level shifters and it can obtain smaller wirelength if we can consider level shifters during floorplanning. [ABSTRACT FROM PUBLISHER] |
