Theoretical limits for signal reflections due to inductance for on-chip interconnections.
| Autor: | Deschacht, D., Servel, G., Huret, F., Paleczny, E., Kennis, P. |
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| Zdroj: | Proceedings of the 2000 International Workshop: System-level Interconnect Prediction; 4/ 8/2000, p55-60, 6p |
| Databáze: | Complementary Index |
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