Clock gating for power optimization in ASIC design cycle theory & practice.
| Autor: | S, Jairam, Rao, Madhusudan, Srinivas, Jithendra, Vishwanath, Parimala, H, Udayakumar, Rao, Jagdish |
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| Zdroj: | Proceeding of the 13th International Symposium: Low Power Electronics & Design; 8/11/2008, p307-308, 2p |
| Databáze: | Complementary Index |
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