Circuit design of a 9ns-HIT-delay 32K byte cache macro.
| Autor: | Nogami, K., Sakurai, T., Sawada, K., Sakaue, K., Miyazawa, Y., Tanaka, S., Hiruta, Y., Katoh, K., Takayanagi, T., Shirotopi, T., Itoh, Y., Uchma, M., Hzuka, T. |
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| Zdroj: | 1989 Symposium on VLSI Circuits, 1989. Digest of Technical Papers; 1989, p45-46, 2p |
| Databáze: | Complementary Index |
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