Topography and Deformation Measurement and FE Modeling applied to substrate-mounted large area wafer-level packages (including stacked dice and TSVs).
| Autor: | Hert, M., Carniello, S., Cassidy, C. |
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| Zdroj: | 2010 17th IEEE International Symposium on the Physical & Failure Analysis of Integrated Circuits (IPFA); 2010, p1-5, 5p |
| Databáze: | Complementary Index |
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