ESD protection scheme using CMOS compatible vertical bipolar transistor for 130 nm CMOS generation.
| Autor: | Okushima, M., Noguchi, K., Sawahata, K., Suzuki, H., Kuroki, S., Koyama, S., Ando, K., Ikezawa, N. |
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| Zdroj: | International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138); 2000, p127-130, 4p |
| Databáze: | Complementary Index |
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