SALVO process for sub-50 nm low-VT replacement gate CMOS with KrF lithography.
| Autor: | Chang, C.-P., Vuang, H.-H., Baker, M.R., Pai, C.S., Klemens, F.P., Miner, J.F., Mansfield, W.M., Kleiman, R.N., Kornbllit, A., Baumann, F.H., Rogers, S.N., Bude, M., Grazul, J.L., Lloyd, E.J., Frei, M., Sorsch, T.W., Cirelli, R., Ferry, E., Bolan, K., Barr, D. |
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| Zdroj: | International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138); 2000, p53-56, 4p |
| Databáze: | Complementary Index |
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