Highly area efficient and cost effective double stacked S3 (stacked single-crystal Si) peripheral CMOS SSTFT and SRAM cell technology for 512M bit density SRAM.
| Autor: | Soon-Moon Jung, Hoon Lim, Wonseok Cho, Hoosung Cho, Chadong Yeo, Yongha Kang, Daegi Bae, Jonghoon Na, Kunho Kwak, Bonghyun Choi, Sungjin Kim, Jaehun Jeong, Youngchul Chang, Jaehoon Jang, Jonghyuk Kim, Kinam Kim, Byung-Il Ryu |
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| Zdroj: | IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004; 2004, p265-268, 4p |
| Databáze: | Complementary Index |
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