Highly scalable sub-50nm vertical double gate trench DRAM cell.
| Autor: | Schloesser, T., Manger, D., Weis, R., Slesazeck, S., Lau, F., Tegen, S., Sesterhenn, M., Muemmler, M., Nuetzel, J., Temmler, D., Kowalski, B., Scheler, U., Stavrev, M., Koehler, D. |
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| Zdroj: | IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004; 2004, p57-60, 4p |
| Databáze: | Complementary Index |
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