FPGA-based implementation of a CFAR processor using Batcher's sort and LUT arithmetic.

Autor:	Seddiq, Y.M., Alshebeili, S.A., Alhumaidi, S.M., Obied, A.M.
Zdroj:	2009 4th International Design & Test Workshop (IDT); 2009, p1-6, 6p
Databáze:	Complementary Index
Externí odkaz:	Zobrazit plný text záznamu