Wide-range fast-lock duty-cycle corrector with offset-tolerant duty-cycle detection scheme for 54nm 7Gb/s GDDR5 DRAM interface.
| Autor: | Shin, Dongsuk, Na, Kwang-Jin, Kwon, Daehan, Kang, Jong-Ho, Song, Taeksang, Jung, Ho-Don, Lee, Woo-Young, Park, Ki-Chon, Park, Jung-Hoon, Joo, Yong-Suk, Cha, Jae-Hoon, Jung, Youngho, Kim, Youngran, Han, Donghoon, Choi, Byoung-Jin, Lee, Geun-Il, Cho, Joo-Hwan, Choi, Young-Jung |
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| Zdroj: | 2009 Symposium on VLSI Circuits; 2009, p138-139, 2p |
| Databáze: | Complementary Index |
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