Managing annealing pattern effects in 45nm low power CMOS technology.
| Autor: | Morin, P., Cacho, F., Beneyton, R., Dumont, B., Bidaud, M., Josse, E., Gallon, C., Ranica, R., Villaret, A., Bianchini, R., Devoivre, T., Serret, E., Binger, R., Barla, K., Haond, M., Colin, A., Bono, H., Chaton, C. |
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| Zdroj: | 2009 Proceedings of the European Solid State Device Research Conference; 2009, p288-291, 4p |
| Databáze: | Complementary Index |
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