Low-power and highly reliable logic gates transistor-level optimizations.
| Autor: | Sulieman, M.H., Beiu, V., Ibrahim, W. |
|---|---|
| Zdroj: | 2010 10th IEEE Conference on Nanotechnology (IEEE-NANO); 2010, p254-257, 4p |
| Databáze: | Complementary Index |
| Externí odkaz: |
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| Autor: | Sulieman, M.H., Beiu, V., Ibrahim, W. |
|---|---|
| Zdroj: | 2010 10th IEEE Conference on Nanotechnology (IEEE-NANO); 2010, p254-257, 4p |
| Databáze: | Complementary Index |
| Externí odkaz: |
|