A 65-nm-CMOS 100-MHz 87%-efficient DC-DC down converter based on dual-die system-in-package integration.
| Autor: | Bergveld, H.J., Nowak, K., Karadi, R., Iochem, S., Ferreira, J., Ledain, S., Pieraerts, E., Pommier, M. |
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| Zdroj: | 2009 IEEE Energy Conversion Congress & Exposition; 2009, p3698-3705, 8p |
| Databáze: | Complementary Index |
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