Loopback architecture for wafer-level at-speed testing of embedded HyperTransportTM processor links.
| Autor: | Loke, A.L.S., Doyle, B.A., Oshima, M.M., Williams, W.L., Lewis, R.G., Wang, C.L., Hanpachern, A., Tucker, K.M., Gurunath, P., Asada, G.C., Lackey, C.O., Wee, T.T., Fang, E.S. |
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| Zdroj: | 2009 IEEE Custom Integrated Circuits Conference; 2009, p605-608, 4p |
| Databáze: | Complementary Index |
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