Synthesizable verification IP to stress test system-on-chip emulation and prototyping platforms.
| Autor: | Shankar, Subramanian Shiva, Shankar, Jayaratnam Siva |
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| Zdroj: | 2011 13th International Symposium on Integrated Circuits (ISIC); 2011, p609-612, 4p |
| Databáze: | Complementary Index |
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