Compact FPGA implementation of 32-bits AES algorithm using Block RAM.
| Autor: | Chi-Wu Huang, Chi-Jeng Chang, Mao-Yuan Lin, Hung-Yun Tai |
|---|---|
| Zdroj: | TENCON 2007 - 2007 IEEE Region 10 Conference; 2007, p1-4, 4p |
| Databáze: | Complementary Index |
| Externí odkaz: |
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| Autor: | Chi-Wu Huang, Chi-Jeng Chang, Mao-Yuan Lin, Hung-Yun Tai |
|---|---|
| Zdroj: | TENCON 2007 - 2007 IEEE Region 10 Conference; 2007, p1-4, 4p |
| Databáze: | Complementary Index |
| Externí odkaz: |
|