Ge deep sub-micron pFETs with etched TaN metal gate on a high-k dielectric, fabricated in a 200mm silicon prototyping line.
| Autor: | De Jaeger, B., Houssa, M., Satta, A., Kubicek, S., Verheyen, P., Van Steenbergen, J., Croon, J., Kaczer, B., Van Elshocht, S., Delabie, A., Kunnen, E., Sleeckx, E., Teerlinck, I., Lindsay, R., Schram, T., Chiarella, T., Degraeve, R., Conard, T., Poortmans, J., Winderickx, G. |
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| Zdroj: | Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850); 2004, p189-192, 4p |
| Databáze: | Complementary Index |
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