Digital delay locked loop with open-loop digital duty cycle corrector for 1.2Gb/s/pin double data rate SDRAM.
| Autor: | Chunseok Jeong, Changsik Yoo, Jae-Jin Lee, Joongsik Kih |
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| Zdroj: | Proceedings of the 30th European Solid-State Circuits Conference; 2004, p379-382, 4p |
| Databáze: | Complementary Index |
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