65nm high performance SRAM technology with 25F2 0.16μm2 S3 (stacked single-crystal Si) SRAM cell, and stacked peripheral SSTFT for ultra high density and high speed applications.
| Autor: | Hoon Lim, Soon-Moon Jung, Youngseop Rah, Taehong Ha, Hanbyung Park, Chulsoon Chang, Wonsuk Cho, Jaikyun Park, Byoungkeun Son, Jaehun Jeong, Hoosung Cho, Bonghyun Choi, Kinam Kim |
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| Zdroj: | Proceedings of 35th European Solid-State Device Research Conference, 2005 (ESSDERC 2005); 2005, p549-552, 4p |
| Databáze: | Complementary Index |
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