Using a hierarchical DfT methodology in high frequency processor designs for improved delay fault testability.
| Autor: | Kessler, M., Kiefer, G., Leenstra, J., Schunemann, K., Schwarz, T., Wunderlich, H.-J. |
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| Zdroj: | Proceedings International Test Conference 2001 (Cat. No.01CH37260); 2001, p461-469, 9p |
| Databáze: | Complementary Index |
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