Hardware/software co-training by FPGA/ASIC synthesis and programming of a RISC microprocessor-core.
| Autor: | Becker, J.E., Bieser, C., Thomas, A., Muller-Glaser, K.D., Becker, J. |
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| Zdroj: | Proceedings 2003 IEEE International Conference on Microelectronic Systems Education. MSE'03; 2003, p134-135, 2p |
| Databáze: | Complementary Index |
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