A Digital PLL with 5-Phase Digital PFD for Low Long-term Jitter Clock Recovery.
| Autor: | Tae-Young Oh, Seung-Hyun Yi, Sung-Hyun Yang, Byong-Chan Lim, Kuk-Tae Hong |
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| Zdroj: | IEEE Custom Integrated Circuits Conference 2006; 2006, p745-748, 4p |
| Databáze: | Complementary Index |
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