Gate-all-around Si-nanowire CMOS inverter logic fabricated using top-down approach.
| Autor: | Buddharaju, K.D., Singh, N., Rustagi, S.C., Teo, S.H.G., Wong, L.Y., Tang, L.J., Tung, C.H., Lo, G.Q., Balasubramanian, N., Kwong, D.L. |
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| Zdroj: | ESSDERC 2007 - 37th European Solid State Device Research Conference; 2007, p303-306, 4p |
| Databáze: | Complementary Index |
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