Impact of stress on various circuit characteristics in 65nm PDSOI technology.
| Autor: | Suryagandh, S., Gupta, M., Zhi-Yuan Wu, Krishnan, S., Pelella, M., Jung-Suk Goo, Thuruthiyil, C., An, J.X., Chen, B.Q., Subba, N., Zamudio, L., Yonemura, J., Icel, A.B. |
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| Zdroj: | ESSDERC 2007 - 37th European Solid State Device Research Conference; 2007, p119-122, 4p |
| Databáze: | Complementary Index |
| Externí odkaz: |
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