VHDL modeling and analysis of error-control specific circuits for multiple-modular redundant systems with concurrent error location capability.
| Autor: | Jiang Jianhui, Min Yinghua, Peng Chenglian |
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| Zdroj: | 2001 4th International Conference on ASIC Proceedings ASICON 2001 (Cat. No.01TH8549); 2001, p570-573, 4p |
| Databáze: | Complementary Index |
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