On the design of power-rail esd clamp circuit with consideration of gate leakage current in 65-nm low-voltage CMOS process.
| Autor: | Ming-Dou Ker, Po-Yen Chiu, Fu-Yi Tsai, Yeong-Jar Chang |
|---|---|
| Zdroj: | 2009 IEEE International Symposium on Circuits & Systems; 2009, p2281-2284, 4p |
| Databáze: | Complementary Index |
| Externí odkaz: |
|