An 8.69 Mvertices/s 278 Mpixels/s tile-based 3d graphics full pipeline with embedded performance counting module, real-time bus tracer and protocol checker for consumer electronics.
| Autor: | Ruei-Ting Gu, Wei-Sheng Huang, Chien-Chou Wang, Wen-Chi Shiue, Tsung-Yu Ho, Chung-Hua Tsai, Tzu-Ching Tien, Da-Jing Zhang-Jian, Sheng-Yu Chiu, Ing-Jer Huang, Yun-Nan Chang, Shen-Fu Hsiao, Jin-Hua Hong, Chung-Nan Lee, Ming-Chao Chiang |
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| Zdroj: | 2008 IEEE International Symposium on VLSI Design, Automation & Test (VLSI-DAT); 2008, p59-62, 4p |
| Databáze: | Complementary Index |
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