A cost-conscious 32nm CMOS platform technology with advanced single exposure lithography and gate-first metal gate/high-k process.
| Autor: | Hasegawa, S., Kitamura, Y., Takahata, K., Okamoto, H., Hirai, T., Miyashita, K., Ishida, T., Aizawa, H., Aota, S., Azuma, A., Fukushima, T., Harakawa, H., Hasegawa, E., Inohara, M., Inumiya, S., Ishizuka, T., Iwamoto, T., Kariya, N., Kojima, K., Komukai, T. |
|---|---|
| Zdroj: | 2008 IEEE International Electron Devices Meeting; 2008, p1-3, 3p |
| Databáze: | Complementary Index |
| Externí odkaz: |
|