Power integrity chip-package-PCB co-simulation for I/O interface of DDR3 high-speed memory.
| Autor: | Hao-Hsiang Chuang, Shu-Jung Wu, Ming-Zhang Hong, Hsu, D., Huang, R., Li Chang Hsiao, Tzong-Lin Wu |
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| Zdroj: | 2008 Electrical Design of Advanced Packaging & Systems Symposium; 2008, p31-34, 4p |
| Databáze: | Complementary Index |
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