A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery.
| Autor: | Harwood, M., Warke, N., Simpson, R., Leslie, T., Amerasekera, A., Batty, S., Colman, D., Carr, E., Gopinathan, V., Hubbins, S., Hunt, P., Joy, A., Khandelwal, P., Killips, B., Krause, T., Lytollis, S., Pickering, A., Saxton, M., Sebastio, D., Swanson, G. |
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| Zdroj: | 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers; 2007, p436-591, 156p |
| Databáze: | Complementary Index |
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