BEOL process integrations with Cu/FSG wiring at 90 nm design-rule DDR DRAM and their effects on yield, refresh time, and wafer-level reliability.
| Autor: | Nohiung Kwak, Sang-Tae Ahn, Hyung-Soon Park, Seo-Min Kim, Jin-Ki Jung, Gyu-Hyun Kim, Geun-Young Choi, Dong-Chul Koo, Tae-Oh Jung, Ja-Chun Ku, Jae-Kwan Jung, Jinwoong Kim, Sungwook Park, Hyunchul Sohn, Soo-Hyun Kim |
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| Zdroj: | 2007 IEEE International Interconnect Technology Conference; 2007, p150-152, 3p |
| Databáze: | Complementary Index |
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