A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST.
| Autor: | Anand, D., Covino, J., Dreibelbis, J., Fifield, J., Gorman, K., Jacunski, M., Paparelli, J., Pomichter, G., Pontius, D., Roberge, M., Sliva, S. |
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| Zdroj: | 2007 IEEE Custom Integrated Circuits Conference; 2007, p795-798, 4p |
| Databáze: | Complementary Index |
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