A complex-envelope based digital phase locked loop with an arctan phase detector implemented on FPGA and performance analysis.
| Autor: | Kandeepan, S., Hashmi, O., Qian Zheng |
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| Zdroj: | 2007 6th International Conference on Information, Communications & Signal Processing; 2007, p1-5, 5p |
| Databáze: | Complementary Index |
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