Implementing a 2-Gbs 1024-bit ½-rate low-density parity-check code decoder in three-dimensional integrated circuits.
| Autor: | Lili Zhou, Wakayama, C., Panda, R., Jangkrajarng, N., Hu, B., Shi, C.-J.R. |
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| Zdroj: | 2007 25th International Conference on Computer Design; 2007, p194-201, 8p |
| Databáze: | Complementary Index |
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