Low Power Sampling Latch for up to 25 Gb/s 2x Oversampling CDR in 90-nm CMOS.
| Autor: | Buren, G.V., Rodoni, L., Kromer, C., Jackel, H., Huber, A., Morf, T. |
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| Zdroj: | 2006 Proceedings of the 32nd European Solid-State Circuits Conference; 2006, p106-109, 4p |
| Databáze: | Complementary Index |
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