Input Capacitance Modeling of Logic Gates for Accurate Static Timing Analysis.
| Autor: | Takeshi Kouno, Masanori Hashimoto, Hidetoshi Onodera |
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| Zdroj: | 2005 IEEE Asian Solid-State Circuits Conference; 2005, p453-456, 4p |
| Databáze: | Complementary Index |
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