Cascaded PLL design for a 90nm CMOS high performance microprocessor.
| Autor: | Wong, K.L., Fayneh, E., Knoll, E., Law, R.H., Lim, C.H., Parker, R.J., Feng Wang, Cangsang Zhao |
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| Zdroj: | 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC; 2003, p422-422, 1p |
| Databáze: | Complementary Index |
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