A 2 Gb/s/pin 4-PAM parallel bus interface with transmit crosstalk cancellation, equalization, and integrating receivers.
| Autor: | Zerbe, J.L., Chau, P.S., Werner, C.W., Stonecypher, W.F., Liaw, H.J., Gong Jong Yeh, Thrush, T.P., Best, S.C., Donnelly, K.S. |
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| Zdroj: | 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177); 2001, p66-432, 3p |
| Databáze: | Complementary Index |
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