Tungsten silicide gate stack optimization for 170-nm DRAM technology.
| Autor: | Rao, V., Morgan, J., Hoesler, W., Barden, J., Karzhavin, Y., Van Holt, P., Petter, R., Ollendorf, H., Christensen, K., Ricks, D. |
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| Zdroj: | 2000 IEEE/SEMI Advanced Semiconductor Manufacturing Conference & Workshop. ASMC 2000 (Cat. No.00CH37072); 2000, p340-346, 7p |
| Databáze: | Complementary Index |
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