Multi-voltage device integration technique for 0.5 μm BiCMOS and DMOS process.

Autor:	Terashima, T., Yamamoto, F., Hatasako, K.
Zdroj:	12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094); 2000, p331-334, 4p
Databáze:	Complementary Index
Externí odkaz:	Zobrazit plný text záznamu