A 56GS/S 6b DAC in 65nm CMOS with 256×6b memory.
| Autor: | Greshishchev, Y.M., Pollex, D., Shing-Chi Wang, Besson, M., Flemeke, P., Szilagyi, S., Aguirre, J., Falt, C., Ben-Hamida, N., Gibbins, R., Schvan, P. |
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| Zdroj: | 2011 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC); 2011, p194-196, 3p |
| Databáze: | Complementary Index |
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