Design, simulation and process optimization of AuInSn low temperature TLP bonding for 3D IC Stacking.
| Autor: | Ling Xie, Won Kyoung Choi, Premachandran, C.S., Selvanayagam, C.S., Ke Wu Bai, Ying Zhi Zeng, Siong Chiew Ong, Ebin Liao, Khairyanto, A., Sekhar, V.N., Thew, S. |
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| Zdroj: | 2011 IEEE 61st Electronic Components & Technology Conference (ECTC); 2011, p279-284, 6p |
| Databáze: | Complementary Index |
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